The present invention relates to a data processing circuit, including a set of processing elements.
Many environments require the real time processing of data. Digital signal processors are often configured to perform multiplications upon data with subsequent arithmetic operations, such as an accumulation, being executed by an arithmetic unit.
In many applications, it is desirable to perform manipulations quickly while at the same time minimising power consumption. Although a great deal of versatility is available through the use of software instructions, such instructions may result in a device taking up valuable processing time while implementing relatively straightforward operations. It is therefore desirable to optimise the provision of specific hardware circuitry such that each device is operating to its optimum level of performance. Additionally, it is desirable to minimise the area taken up by such circuitry.